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Microchip Technology /ATSAME51J18A /QSPI /INTENCLR

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Interpret as INTENCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXC)RXC 0 (DRE)DRE 0 (TXC)TXC 0 (ERROR)ERROR 0 (CSRISE)CSRISE 0 (INSTREND)INSTREND

Description

Interrupt Enable Clear

Fields

RXC

Receive Data Register Full Interrupt Disable
DRE

Transmit Data Register Empty Interrupt Disable
TXC

Transmission Complete Interrupt Disable
ERROR

Overrun Error Interrupt Disable
CSRISE

Chip Select Rise Interrupt Disable
INSTREND

Instruction End Interrupt Disable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data